DEN3=0, IEN2=0, DEN2=0, IEN3=0, EDGE2=00, STS3=0, EDGE3=00, STS2=0
Crossbar A Control Register 1
DEN2 | DMA Enable for XBAR_OUT2 0 (0): DMA disabled 1 (1): DMA enabled |
IEN2 | Interrupt Enable for XBAR_OUT2 0 (0): Interrupt disabled 1 (1): Interrupt enabled |
EDGE2 | Active edge for edge detection on XBAR_OUT2 0 (00): STS2 never asserts 1 (01): STS2 asserts on rising edges of XBAR_OUT2 2 (10): STS2 asserts on falling edges of XBAR_OUT2 3 (11): STS2 asserts on rising and falling edges of XBAR_OUT2 |
STS2 | Edge detection status for XBAR_OUT2 0 (0): Active edge not yet detected on XBAR_OUT2 1 (1): Active edge detected on XBAR_OUT2 |
DEN3 | DMA Enable for XBAR_OUT3 0 (0): DMA disabled 1 (1): DMA enabled |
IEN3 | Interrupt Enable for XBAR_OUT3 0 (0): Interrupt disabled 1 (1): Interrupt enabled |
EDGE3 | Active edge for edge detection on XBAR_OUT3 0 (00): STS3 never asserts 1 (01): STS3 asserts on rising edges of XBAR_OUT3 2 (10): STS3 asserts on falling edges of XBAR_OUT3 3 (11): STS3 asserts on rising and falling edges of XBAR_OUT3 |
STS3 | Edge detection status for XBAR_OUT3 0 (0): Active edge not yet detected on XBAR_OUT3 1 (1): Active edge detected on XBAR_OUT3 |